Rydev remains steadfast in its commitment to bolstering Costa Rica’s semiconductor supply chain. In alignment with this goal, our COO, Dr. Ronny García Ramírez, has been actively participating in initiatives…
Our COO, Dr. Ronny García Ramírez, represented Rydev at the IEEE 42nd Central America and Panama Convention (CONCAPAN XLII), held from November 27–29, 2024, in San José, Costa Rica. During…
We had the pleasure of having our CEO, Guillermo Güichal, visiting with us this past November 6th and 7th, where we shared strategic meetings on our growth plans for 2025.…
Two of our senior IC verification specialists, Kaleb Alfaro and David Solórzano, participated in DVCON Europe 2024 on October 15 and 16. “It was a great opportunity to learn from…
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com After doing all the modifications described in parts I and II of this blog, we ended up at a dead-end. Errors in…
As a Latin American company intent on producing its own research and development, and our continuing collaboration with our commercial and academic partners in the production of advanced ASIC designs,…
During the first week of October, we had the honor of having our VP of Business Development, Dr. Alfonso Chacón-Rodríguez, participate as IEEE-CAS Industry Distinguished Lecturer at the “CANELOS: CAD…
August and September were a couple of busy months here in Rydev. Our General Engineering Manager, Renato Rimolo-Donadio, attended the "International Technology Security and Innovation. (ITSI) Workforce Accelerator Kick-Off Session"…
By Ricardo Gallo. ASIC design engineer and David Medina, Engineering Intern Access to RTL design and verification proprietary software is very complicated for small design houses such as ours. And…
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com Testing verification featuresAfter working around the problems with randomization on Verilator, we ran more experiments on some of the most common features one…