Visit to Costa Rica from our CEO
We had the pleasure of having our CEO, Guillermo Güichal, visiting with us this past November 6th and 7th, where we shared strategic meetings on our growth plans for 2025.…
Rydev was at DVCON Europe 2024
Two of our senior IC verification specialists, Kaleb Alfaro and David Solórzano, participated in DVCON Europe 2024 on October 15 and 16. “It was a great opportunity to learn from…
Some tips on working around UVM limitations in Verilator. Part 3
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com After doing all the modifications described in parts I and II of this blog, we ended up at a dead-end. Errors in…
Rydev participates at the Sandia Labs course “Safeguarding Research in Semiconductors and Microelectronics”
As a Latin American company intent on producing its own research and development, and our continuing collaboration with our commercial and academic partners in the production of advanced ASIC designs,…
IEEE-CAS Distinguished Lecture by our VP of Business Development at USM Valparaíso, Chile
During the first week of October, we had the honor of having our VP of Business Development, Dr. Alfonso Chacón-Rodríguez, participate as IEEE-CAS Industry Distinguished Lecturer at the “CANELOS: CAD…
A couple of busy months for Rydev!
August and September were a couple of busy months here in Rydev. Our General Engineering Manager, Renato Rimolo-Donadio, attended the "International Technology Security and Innovation. (ITSI) Workforce Accelerator Kick-Off Session"…
Admin using tablet in server hub to maintenance artificial intelligence neural networks simulating human thought processes. Cloud computing business worker does checkup on AI systems
DSIM: A SaaS solution for your RTL verification needs
By Ricardo Gallo. ASIC design engineer and David Medina, Engineering Intern Access to RTL design and verification proprietary software is very complicated for small design houses such as ours. And…
Some tips on working around UVM limitations in Verilator. Part 2
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com Testing verification featuresAfter working around the problems with randomization on Verilator, we ran more experiments on some of the most common features one…