ASIC Verification

Our verification engineers have mastered various strategies and guidelines, enabling customers to achieve rapid and reliable closure of the verification process.

Unmatched Expertise in ASIC Design and Verification

An ineffective verification strategy can consume valuable time and resources. Therefore, it is crucial to rely on expertise and experience. With over 15 years of experience and a profound understanding of the verification discipline, we recognize that the cornerstone of successful ASIC design and development lies in the careful selection of effective verification criteria.

Achieving Rapid and Reliable ASIC Verification

Our verification engineers have mastered various ASIC verification strategies and guidelines, enabling customers to achieve rapid and reliable closure of the verification process for even the most complex ASICs.

Capabilities

Advanced IP and SOC Verification with Modern Methodologies: From C/C++ and SV-UVM to Release Planning and Management:

  • IP and SOC-level Verification using C/C++, SV-UVM methodologies (UVM 1.1, 1.2) 
  • Test plan development and implementation, using modern project management techniques (Jira) to achieve Functional and Code Coverage goals 
  • Power-aware verification 
  • Gate-level simulations and regression management
  • Version Control Systems
  • SV assertions

Sample project

Delivering High Quality Service

  • Migration of legacy UVM/OVM environments to new environments for two new ASIC designs
  • Generation and implementation of the pre-silicon test plan (blocks and full-chip), including execution and management (Jira and GitHub)
  • Cadence’s VIPs integration for an AlphaWave PCIe controller (5Gen), I2C and SPI-IP interfaces, into the verification flow for both ASICs.
  • System integration and verification of a Tensilica microcontroller IP including integration of SRAM.
  • Platform-level validation, Gate level simulations and FPGA emulation of the controller (using new firmware).