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Reading time: 10 min Audience VLSI engineers & design managers Keywords: RTL, DV, UVM, AI agents The integrated circuit industry has always been defined by
By Jose Villalobos As System-on-Chip (SoC) architectures migrate toward more complex designs, like the Network-on-Chip (NoC) fabrics and multi-path access hierarchies, traditional UVM verification often
By Renato Rimolo-Donadio, renato.rimolo@rydevinc.com S-parameters (or scattering parameters) are the most used representation for interconnect models in the frequency domain, whether derived from analytical models,
By Kaleb Alfaro. ASIC verification engineer at Rydev kaleb.alfaro@rydevinc.com Most of the time we do not give much thought about the steps that our EDA
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com After doing all the modifications described in parts I and II of this blog, we ended up
By Ricardo Gallo. ASIC design engineer and David Medina, Engineering Intern Access to RTL design and verification proprietary software is very complicated for small design
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com Testing verification features After working around the problems with randomization on Verilator, we ran more experiments on some
By Susana Sevilla. ASIC verification engineer at Rydev susana.sevilla@rydevinc.com Part 1 Introduction Verilator is a free cycle-based simulator tool used for Verilog/SystemVerilog RTL design
By David Solórzano. ASIC verification engineer at Rydev david.solorzano@rydevinc.com Let’s face it, VCS and Verdi are awesome tools but, precisely because of all their