Reading time: 10 min
Audience VLSI engineers & design managers
Keywords: RTL, DV, UVM, AI agents
The integrated circuit industry has always been defined by complexity. What is changing now is who — or what — manages that complexity, and how far we can trust it to go on its own. Can AI really accelerate ASIC development without putting IP, verification, quality or engineering judgement at risk?
Here’s Rydev’s vision and experience in the integration of AI into the world of ASIC design.
INDUSTRY CONTEXT
A shifting landscape
For decades, VLSI design has been labor-intensive by necessity. Each stage of the flow — from microarchitecture decisions through RTL, verification, physical implementation, and sign-off — demands deep domain expertise and judgment calls that can only come from engineers who understand both the silicon and the intended application. Generative AI entered this space first as a novelty, then as a productivity multiplier.
The decision on whether a design choice is architecturally correct or not— not just syntactically valid, still relies on human intervention. Human oversight remains the indispensable layer, not as a workaround for AI limitations but as the engineering discipline the process requires.
Individual AI assistants became useful for generating boilerplate, answering documentation queries, and accelerating isolated tasks. Today, the frontier has moved: the real value is no longer in isolated AI tools but in structured, orchestrated AI workflows — networks of specialized agents coordinated to tackle entire design stages.
Adoption, however, follows a rational calculus: economic cost, IP containment, and integration effort. No design house will deploy a multi- agent pipeline if it puts customer IP at risk, or if the integration overhead dwarfs the productivity gain. On the other hand, the cost of tokens quickly consumes allocated budget, raising the question of ROI and the comparative expense of AI vs. hiring.
This distinction matters. AI models and tools still run into hallucinations (which reduce as the model refines), however, the concern is always present. Hitting coverage metrics is not the same as verifying that a design does what its architects intended. Human oversight remains the indispensable layer — not as a workaround for AI limitations, but as the
engineering discipline the process requires. As technology evolves, this panorama will change, but as of now: AI solutions are of great help in localized activities while still requiring the expert guidance and voice of experience.
USE CASES
RTL development: the orchestrator model in practice
RTL coding was among the earliest beneficiaries of LLM-based assistance. Module stubs, FSM skeletons, bus interface logic — these are tasks where AI produces a credible first draft quickly. The real architectural shift, though, is the emergence of the orchestrator model.
In this model, a centralized, data-driven orchestrator agent coordinates a constellation of specialized sub-agents: an RTL writer, a code reviewer, a debug agent, a specification planner, a testbench author. Each agent operates within a narrow, well-defined scope. The orchestrator tracks dependencies, manages context, and routes outputs between agents.
Even with this architecture fully in place, the exit criteria for each stage must be validated by human engineers with expert criteria. A block that passes all automated checks but violates a microarchitecture assumption — clock domain assumptions, pipeline depth, reset strategy — can propagate silently through the flow until it becomes an expensive respin. Architecture specification is the ground truth; agents optimize toward it, but only engineers can define and defend it, this has been our mantra at Rydev in order to ensure product quality, adherence to specification while accelerating execution withouth compromising results.
Design verification: structured AI inside the UVM flow
Design verification is where multi-agent AI shows perhaps its most compelling value — and also its clearest boundary. The UVM methodology is inherently structured: environments, agents, scoreboards, coverage collectors, and sequences each have defined responsibilities and interfaces. That structure maps naturally onto a multi-agent decomposition.
A typical AI-augmented DV flow begins with a text-based device architecture as the seed. From there, agents assist the DV team in generating the verification plan: the coverage strategy, the assertion library scope, the environment topology, and the agent configuration. This output is then reviewed — and approved — jointly by DV and RTL engineers.
The alignment between verification strategy and intended design is not a formality. It is the step where the entire downstream effort is either validated or compromised. No agent should own that decision.
Once the strategy is agreed, the flow opens. Carefully designed prompts guide agents to generate UVM components: register models, interface agents, scoreboards, constraint classes, and coverage groups. Each artifact is reviewed before integration. The cumulative effect is a material acceleration of environment build-out — without sacrificing the engineering rigor that makes verification meaningful.
What remains firmly in human hands: the definition of what “correct” behavior means for the DUT, the interpretation of corner-case failures, and the call on when functional coverage is truly closed versus merely numerically satisfied.
OUR PERSPECTIVE
Value delivery is still the standard
Rydev delivers chips that get built. That simple statement carries weight: a design that reaches tape-out with an undetected functional error is not a productivity success, regardless of how efficiently it was produced.
Our adoption of AI-augmented workflows is measured against that standard. We use multi-agent orchestration where it compresses schedule and reduces rework on well-defined tasks. We maintain rigorous engineering oversight where it ensures correctness. And we treat IP containment not as a compliance checkbox but as a structural requirement of every pipeline we deploy.
The conversation in the industry right now tends to focus on what AI can do. Our focus is on what it should own — and what it should hand back to the engineer. Getting that boundary right is what separates a productivity tool from a liability. For projects involving fabrication using advanced nodes, high-speed SerDes, or satellite-grade reliability requirements, that boundary is drawn with deliberate care. The designs are too costly, and the customer’s confidence too important, to treat AI autonomy as anything other than a precisely scoped engineering decision.
Interested in how we approach AI-augmented VLSI workflows for your project?
Marco Vindas
About the author: Marco Vindas is a verification engineering lead at Rydev. He holds an Electronics Engineering degree from TEC (Tecnológico de Costa Rica) and solid experience in the field of complex IP design and verification.