At Rydev, we believe our success stems from the exceptional quality of our team and their unwavering commitment to excellence. That’s why we continuously invest in enhancing their technical skills—while, of course, making sure we have a great time along the way.

Last December, we held a refresher session at our Costa Rica site on key concepts behind the latest SystemVerilog specifications for RTL design, focusing on its OOP capabilities for efficient testbenching. Our RTL designers, Felipe Herrero and Ricardo Gallo (joining remotely from our Argentina site), shared valuable insights, practical examples, and best practices for writing efficient, synthesizable code. They also provided guidance on setting up concise yet powerful test fixtures that leverage SystemVerilog’s full potential, including threads, mailboxes, and other advanced constructs.

Following that, our CTO, Ronny García, led a hands-on workshop on essential verification techniques, covering topics such as randomized and layered testbench architectures in SystemVerilog, the different layers within these environments, UVM hierarchy, UVM TLM, and the UVM factory, among others.

Of course, we wrapped up the session with a well-deserved gourmet pizza tasting.

Stay tuned—we’ll be diving deeper into these topics in upcoming blog posts!