Our COO, Dr. Ronny García Ramírez, represented Rydev at the IEEE 42nd Central America and Panama Convention (CONCAPAN XLII), held from November 27–29, 2024, in San José, Costa Rica. During the event, he engaged with numerous researchers and professionals from the region, fostering meaningful connections and knowledge exchange.

Dr. García also participated in the technical sessions hosted by the local chapter of the Circuits and Systems Society, where he presented the paper “Using Pulsed-Latch Scan Chains for Non-Destructive ASIC Testing”. This work, coauthored with Bernardo Rodriguez-Hall, Dr. Renato Rimolo Donadio (General Engineering Manager), and Dr. Alfonso Chacón-Rodríguez (CFO), introduces an innovative approach for non-destructive testing of ASICs.

The proposed methodology leverages pulsed-latch scan chains paired with a self-generated clock signal, eliminating the need for a full synthesis of a scan clock tree and mitigating the high current spikes that occur during simultaneous register displacement in traditional scanning methods. The approach not only ensures non-destructive testing but also achieves remarkable results: a 47% reduction in power consumption during data shifts compared to shadow and standard flip-flop-based scan chains, with only a 9% area increase compared to the original RTL design.

The paper will soon be available in the IEEE database. Stay tuned—we’ll share the link as soon as it’s published!