Rydev is proud to announce its admission into SEMI and the Electronic System Design Alliance (ESDA), a SEMI Technology Coalition. The appointment was formally announced in SEMI’s official press release on July 31,…
By Kaleb Alfaro. ASIC verification engineer at Rydev kaleb.alfaro@rydevinc.com Most of the time we do not give much thought about the steps that our EDA tools have to go through…
Rydev was present at the student week, organized by the Association of Students of Electronic Engineering, Cartago campus, of the Tecnológico de Costa Rica. For three days, our engineers held…
By Susana Sevilla. ASIC verification engineer at Rydev susana.sevilla@rydevinc.com Part 1 Introduction Verilator is a free cycle-based simulator tool used for Verilog/SystemVerilog RTL design and verification ( https://www.veripool.org/verilator/). While…
By David Solórzano. ASIC verification engineer at Rydev david.solorzano@rydevinc.com Let’s face it, VCS and Verdi are awesome tools but, precisely because of all their power and extensive features, sometimes…