How HDL simulations are compiled
Most of the time we do not give much thought about the steps that our EDA tools have to go through to run a simple testbench simulation. Starting from a…
Rydev present at Student Week in Electronics Engineering
Rydev was present at the student week, organized by the Association of Students of Electronic Engineering, Cartago campus, of the Tecnológico de Costa Rica. For three days, our engineers held…
Some tips on working around UVM limitations in Verilator. Part 1
By Susana Sevilla. ASIC verification engineer at Rydev susana.sevilla@rydevinc.com Part 1 Introduction Verilator is a free cycle-based simulator tool used for Verilog/SystemVerilog RTL design and verification ( https://www.veripool.org/verilator/). While…
Basic switches for getting the most out of coverage reports in Synopsys VCS and Verdi
By David Solórzano. ASIC verification engineer at Rydev david.solorzano@rydevinc.com Let’s face it, VCS and Verdi are awesome tools but, precisely because of all their power and extensive features, sometimes…