August and September were a couple of busy months here in Rydev. Our General Engineering Manager, Renato Rimolo-Donadio, attended the "International Technology Security and Innovation. (ITSI) Workforce Accelerator Kick-Off Session"…
By Ricardo Gallo. ASIC design engineer and David Medina, Engineering Intern Access to RTL design and verification proprietary software is very complicated for small design houses such as ours. And…
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com Testing verification featuresAfter working around the problems with randomization on Verilator, we ran more experiments on some of the most common features one…