What does it take to ensure first-silicon success in today’s most demanding ASICs?

At IEEE LASCAS 2026 in Arequipa, Peru, Rydev’s CEO, Alfonso Chacón-Rodríguez, addressed this question head-on during his keynote at the plenary session. His talk, “Challenges for the Verification of High-Speed Interfaces in High-Performance Computing ASICs,” explored the growing complexity of verification in an era where performance boundaries are constantly being redefined.

Co-developed with Renato Rimolo, Rydev’s General Engineering Manager, the presentation drew from real-world industry experience—working at the edge of innovation with advanced ASICs. It connected three decades of evolution in high-speed interfaces with today’s need for smarter, more scalable verification strategies to manage multimillion gate designs.
Because in this industry, success is no longer about design alone—it’s about getting it right the first time.