By Susana Sevilla. ASIC verification engineer at Rydev
susana.sevilla@rydevinc.com

Part 1
Introduction
Verilator is a free cycle-based simulator tool used for Verilog/SystemVerilog RTL
design and verification ( https://www.veripool.org/verilator/). While not supporting 4-state
signals, Verilator can provide efficient verification with a fairly decent coverage of the
current SystemVerilog standard (something that another popular simulator, Icarus,
https://steveicarus.github.io/iverilog/, cannot do). Verilator developers have been
working hard to fully give support to UVM methodology, since this one has become a
major functional verification standard in the ASIC design cycle. As of today, Verilator
supports several UVM features that run for very simple environments. But since UVM is
still not fully supported, these extensions have not been officially added to Verilator.
Anyway, one can play around some of the tool’s limitations and still build a fairly decent
verification framework for small projects, for being able to test these features it is
necessary to work with the additional UVM branch that is under debugging.

Randomization

One of the major drawbacks about Verilator is that it does not have a very
friendly relationship with randomization and constraints. Initially, Verilator only allowed
basic randomization by ignoring every constraint. A second approach regarding
randomization was implemented in 2022, with the introduction of the external library

CRAVE (Constrained Random Verification Environment). Yet CRAVE has not received
any updates for several years and that it is a quite heavy library when incorporated into
Verilator. This means that current Verilator’s repositories master branch has not
incorporated constrained randomization for the time being.
In March 2023 a new approach was added to Verilator, using an external open
solver (suggested ones: z3, cvc4 or cvc5) which can be chosen for solving random
constraints. One can now solve simple arithmetic and logic expressions, leaving aside
momentarily complex constraints. In some cases, workarounds exist to have the
environment simulate in the expected way. Yet, the next features that are still not
supported:

● Turning on/off constraints
● Arrays and complex variables randomization
● Soft constraints (they are treated as hard without a warning)
● Conditional constraints
● Method “randomize() with {}”
I’ve found that the main workaround is to use the $urandom and $urandomrange
commands for generating values in the sequence and, after the randomize command,
assign the values to the generated item. In the case of arrays, the same approach can
be used but with the help of a loop that repeats the process based on the array size.
In part 2 of this blog, I’ll show some of the new features introduced in October 2023 for
the tool, and give some examples on basic verification environments using Verilator