## vlog makes the preprocessing and compilation steps for verilog/systemverilog files
vlogan -sv <path_to_file>/design.sv <path_to_file>/tb.sv
## vcs makes the elaboration steps. It takes the binary structures created from the compilation step previously and build it on top of it the simulation executable 
vcs -s <name_of_elaboration> top_tb -timescale 1ns/1ps
## run simulation
work_dir/simv SZsd

				
	
		
## vlog makes the preprocessing and compilation steps for verilog/systemverilog files
vlogan -sv <path_to_file>/design.sv <path_to_file>/tb.sv
## vcs makes the elaboration steps. It takes the binary structures created from the compilation step previously and build it on top of it the simulation executable 
vcs -s <name_of_elaboration> top_tb -timescale 1ns/1ps
## run simulation
work_dir/simv