Rydev was present at the student week, organized by the Association of Students of Electronic Engineering, Cartago campus, of the Tecnológico de Costa Rica. For three days, our engineers held talks with students on topics related to the design and verification of integrated circuits.

Ing. Ronny Zárate gave a talk showing the complete design of a mixed-signal integrated circuit that was developed for a client, and as part of his master’s thesis in Electronics. In this talk, Ing. Zárate explained the different parts of the IC design flow, from the algorithmic conception, through the design of the circuits, their simulations and layout for manufacturing, to the tests designed for the post-silicon tests that ensure a chip ready for industrial production.

On the other hand, Ing. Kaleb Alfaro, gave a workshop on the bases of SystemVerilog for digital design, supported by our intern Mr. David Medina. Some basic tutorials on SV were offered, and attendees were also shown how to implement digital solutions on commercial FPGAs, using a free flow of simulation and synthesis tools.

In parallel, we had a small stand where Eng. Edgar Solera chatted with students about what we do at Rydev, what skills are needed to work with us designing and testing integrated circuits, and how to contact us for those interested in joining our company as engineers.

We thank Geovanny Mejía and the other members of AESETEC for inviting us to share this space with future electronics engineers.