By Ricardo Gallo. ASIC design engineer and David Medina, Engineering Intern Access to RTL design and verification proprietary software is very complicated for small design
By Susana Sevilla. ASIC verification engineer at Rydevsusana.sevilla@rydevinc.com Testing verification features After working around the problems with randomization on Verilator, we ran more experiments on some
By Susana Sevilla. ASIC verification engineer at Rydev susana.sevilla@rydevinc.com Part 1 Introduction Verilator is a free cycle-based simulator tool used for Verilog/SystemVerilog RTL design
By David Solórzano. ASIC verification engineer at Rydev david.solorzano@rydevinc.com Let’s face it, VCS and Verdi are awesome tools but, precisely because of all their