ASIC Design

We have a proven track record spanning various industries, notably excelling in high-speed communications and data processing.

Experience in Digital ASIC Design

We offer a seasoned digital ASIC design team boasting over 25 years of collective experience and a remarkable portfolio of more than 50 tape-outs ranging from 180 nm to 3 nm nodes. Complemented by a proficient management team with over 15 years in the microelectronics and SoC solutions industry, we offer unparalleled expertise.

Agile and Client-Centric

Our methodology is agile and client-centric, seamlessly aligning with the unique requirements of each project and facilitating a smooth transition from meticulous procedures to swift developments.

We have a proven track record spanning various industries, notably excelling in high-speed communications and data processing.

Versatile and Expert Team in Programming

Our adept staff is proficient in a wide array of programming languages and tools, including Verilog, System Verilog, VHDL, HLS, and scripting languages such as TCL and Python, along with proficiency in C/C++. Additionally, they are well-versed in both frontend and backend flows from Synopsys, Cadence, and Siemens.

Architectural Specification
RTL logic and physical synthesis
SoC and sub-system integration
Ip block design and development
Low-power design & checks & automated property checks
Lint, CDC
DFT insertion ATPG
Clock and reset design, clock gating, UPF
Post-silicon testing writing

Languages

  • Verilog
  • System Verilog
  • VHDL
  • HLS
  • Scripting (TCL, Python,…)
  • C/C++
  • High Level Languages
  • Matlab

Processes

  • CMOS HV 350nm, 180nm, XFAB
  • CMOS 180nm, 130nm, Global Foundries
  • CMOS 65nm down to 3nm, Intel, TSMC

Interfaces

  • HSIO Protocols (PCIe, OmniPath), AMBA protocols (AXI/AHB/APB)
  • High speed SERDES interfacing
  • Memory interfaces (DDRx/LPDDRx)
  • Low-speed peripheral interfaces (I2C, SPI, UART, MDIO, I2S)

Sample project

Delivering High Quality Service

Two ASIC designs of more than 100 million gates each, on a 7 nm TSMC process.

  • Delivered entirely new micro-architecture definition and RTL code for new features in Tx/Rx interfaces including congestion control, port sub-division and virtual lane management (while maintaining compatibility to previous generation ASICs)
  • Expanded legacy data crossbar to accommodate new speed and data formats with backwards compatibility
  • Enhanced data throughput in legacy TX/RX ports with backwards compatibility
  • RTL code developed for a new ARM-based general control manager including integration of SRAM, PVT and proprietary blocks.
  • RTL interface to AlphaWave 100 Gbps SERDES, including new FEC modules.
  • Drove the relation with backend provider on DFT, floorplanning, place & route for both ASICs
  • Synthesis verification (all blocks) including post Place & Route timing and power closure in coordination with backend providers.
  • ECO insertion